/* ==========================================================================================================
   = Project     :  Avenue City FPGA
   = Title       :  level__sync
   = File        :  level__sync.v
   ==========================================================================================================
   = Author      :  Du Wang, Reid McClain
   = Division    :  BDE SH
   = E-mail      :  du.wang@intel.com
   ==========================================================================================================
   = Updated by  :  
   = Division    :  
   = E-mail      :  
   ==========================================================================================================
   = Description :  cdc 1 bit data 

   = Constraints :  
   
   = Notes       :  
   
   ==========================================================================================================
   = Revisions   :  Sep 12, 2021;    0.1; Initial release
   ========================================================================================================== */

                
module level_sync
(
input wire  clk,
input wire  signal_in,

output reg  signal_sync
);

reg     signal_meta;

always @(posedge clk) begin
    signal_meta <=  signal_in;
    signal_sync <=  signal_meta;
end

endmodule
